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Low-Cost, 308MHz, 315MHz, and 433.92MHz
FSK Transceiver with Fractional-N PLL
Pin Description
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
NAME
PAVDD
ROUT
TX/RX1
TX/RX2
PAOUT
AVDD
LNAIN
LNASRC
LNAOUT
MIXIN+
MIXIN-
MIXOUT
IFIN-
IFIN+
PDMIN
PDMAX
DS-
DS+
OP+
DF
RSSI
T/ R
ENABLE
DATA
N.C.
DVDD
HVIN
FUNCTION
Power-Amplifier Supply Voltage. Bypass to GND with 0.01μF and 220pF capacitors placed as close
as possible to the pin.
Envelope-Shaping Output. ROUT controls the power-amplifier envelope’s rise and fall times. Connect
ROUT to the PA pullup inductor or optional power-adjust resistor. Bypass the inductor to GND as
close as possible to the inductor with 680pF and 220pF capacitors as shown in the Typical
Application Circuit .
Transmit/Receive Switch Throw. Drive T/ R high to short TX/RX1 to TX/RX2. Drive T/ R low to disconnect
TX/RX1 from TX/RX2. Functionally identical to TX/RX2.
Transmit/Receive Switch Pole. Typically connected to ground. See the Typical Application Circuit .
Power-Amplifier Output. Requires a pullup inductor to the supply voltage (or ROUT if envelope
shaping is desired), which can be part of the output-matching network to an antenna.
Analog Power-Supply Voltage. AVDD is connected to an on-chip +3.0V regulator in 5V operation.
Bypass AVDD to GND with a 0.1μF and 220pF capacitor placed as close as possible to the pin.
Low-Noise Amplifier Input. Must be AC-coupled.
Low-Noise Amplifier Source for External Inductive Degeneration. Connect an inductor to GND to set
the LNA input impedance.
Low-Noise Amplifier Output. Must be connected to AVDD through a parallel LC tank filter. AC-couple
to MIXIN+.
Noninverting Mixer Input. Must be AC-coupled to the LNA output.
Inverting Mixer Input. Bypass to AVDD with a capacitor as close as possible to the LNA LC tank filter.
330 ? Mixer Output. Connect to the input of the 10.7MHz filter.
Inverting 330 ? IF Limiter Amplifier Input. Bypass to GND with a capacitor.
Noninverting 330 ? IF Limiter Amplifier Input. Connect to the output of the 10.7MHz IF filter.
Minimum-Level Peak Detector for Demodulator Output
Maximum-Level Peak Detector for Demodulator Output
Inverting Data Slicer Input
Noninverting Data Slicer Input
Noninverting Op-Amp Input for the Sallen-Key Data Filter
Data-Filter Feedback Node. Input for the feedback capacitor of the Sallen-Key data filter.
Buffered Received-Signal-Strength-Indicator Output
Transmit/ Receive . Drive high to put the device in transmit mode. Drive low or leave unconnected to
put the device in receive mode. It is internally pulled down.
Enable. Drive high for normal operation. Drive low or leave unconnected to put the device into
shutdown mode.
Receiver Data Output/Transmitter Data Input
No Connection. Do not connect to this pin.
Digital Power-Supply Voltage. Bypass to GND with a 0.01μF and 220pF capacitor placed as close as
possible to the pin.
High-Voltage Supply Input. For 3V operation, connect HVIN to AVDD, PAVDD, and DVDD. For 5V
operation, connect only HVIN to 5V. Bypass HVIN to GND with a 0.01μF and 220pF capacitor placed
as close as possible to the pin.
10
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